1. Field of Invention
The present invention relates to ferroelectric storage apparatuses, driving methods therefor, and driving circuits therefor.
2. Description of Related Art
Ferroelectric storage apparatuses having ferroelectric capacitors as storage elements may serve as memory devices to possibly substitute for related art memories. This may be possible because the ferroelectric storage apparatuses have an operation speed that is as fast as DRAMs and are non-volatile as flash memories.
The related art ferroelectric storage apparatuses include active ferroelectric memories which have 1T/1C cells, each of which has one transistor and one capacitor (ferroelectric) or 2T/2C cells, each of which has a 1T/1C cell and a reference cell. Since there is a limit on the level of integration of 1T/1C cells and 2T/2C cells, a smaller memory-element structure is advantageous in terms of future high integration.
Since ferroelectric materials themselves have a storage holding function, and a memory operation is possible only with ferroelectric capacitors, a structure (1C cell) in which a memory cell is formed of one ferroelectric capacitor only is disclosed in Japanese Unexamined Patent Application Publication No. Hei-9-116107 and PCT Japanese Translation Patent Publication No. 2001-515256.
Since an unnecessary voltage is applied during a non-selection period in the 1C-cell structure, however, the data may deteriorate to cause disturbance finally in which the storage state cannot be determined. Therefore, the related art 1C-cell structure is not practical.
The present invention provides ferroelectric storage apparatuses which can reduce or prevent the disturbance, driving methods therefor, and driving circuits therefor.
In a ferroelectric storage apparatus, a driving method therefor, and a driving circuit therefor according to each aspect of the present invention, an operation step (operation mode) of applying one of data reading, data re-writing, and data writing to at least one selected cell among a plurality of ferroelectric memory cells formed at the intersections of a plurality of word lines and a plurality of bit lines is performed. A disturbance prevention step (disturbance prevention mode) of applying a voltage to each of the plurality of ferroelectric memory cells in an electric-field direction in which the stored data of each ferroelectric memory cell is not inverted is performed after the operation step is executed at least once.
Therefore, a voltage is always applied to not-selected cells at a certain frequency in an electric-field direction in which the stored data of the not-selected cells is not inverted, and data deterioration is reduced or suppressed.
The present invention is especially suited to so-called crossing-point or passive ferroelectric storage apparatuses in which each of the plurality of ferroelectric memory cells is formed of a ferroelectric capacitor only. This is because, in this case, although a voltage may be applied to the not-selected cell in an electric-field direction in which the stored data of the not-selected cells is inverted, when the operation step is applied to the selected cell, the disturbance prevention step reduces or prevents a voltage from being continuously applied to the not-selected cells in the electric-field direction in which the stored data of the non-selected cells is inverted.
In the operation step, one of a first-polarity selection voltage or a second-polarity selection voltage is applied to the at least one selected cell, and one or both of a first-polarity non-selection voltage and a second-polarity non-selection voltage is applied to not-selected cells. In the disturbance prevention step performed thereafter, the first-polarity non-selection voltage and the second-polarity non-selection voltage may be alternately applied to each of the plurality of ferroelectric memory cells.
With this, irrespective of whether the stored data of each memory cell is xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d, a voltage is always applied to all memory cells periodically in an electric-field direction in which the stored data of all the memory cells is not inverted, and data deterioration is reduced or suppressed.
A ferroelectric storage apparatus according to one aspect of the present invention has a structure which includes a plurality of word lines disposed in parallel to each other; a plurality of bit lines disposed in parallel to each other and intersecting with the plurality of word lines; a plurality of ferroelectric memory cells formed at the intersections of the plurality of word lines and the plurality of bit lines; a word-line driver to drive the plurality of word lines; and a bit-line driver to drive the plurality of bit lines. In a driving circuit for a ferroelectric storage apparatus, according to another aspect of the present invention, the word-line driver and the bit-line driver of the above-described ferroelectric storage apparatus are disposed. The method described above according to the present invention is performed also in the ferroelectric storage apparatuses and the driving circuit.